[1] DRAM Translation Layer: Software‐Transparent DRAM Power Savings for Disaggregated Memory, Jin, W., Jang, W., Park, H., Lee, J., Kim, S., & Lee, J. W., In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA), 2023, June.

Graduate Research Assistant

• Advised by Prof. Nam Sung Kim, FAST Lab @ UIUC
• Analyzing various LLC interference patterns with the presence of multiple I/O devices in the real system
• Reverse-engineering Intel SkyLake cache hierarchy, focused on the non-inclusiveness and the directory structure
• Implemented the DMA leakage \& QoS aware LLC management system
• Manuscript in progress to the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) , 2025

Undergraduate Researcher

• Advised by Prof. Jae W. Lee, Architecture and Code Optimization Lab @ SNU
• Conducted experiment scheduling virtual machines running Cloudsuite 4.0 on an actual machine configuration that can sufficiently represent the major features of the suggested non-configurable system
• Proposed estimation methodology for performance and DRAM power metrics of suggested system, where metrics are obtained using PCM(Performance Counter Monitor)
• Fine-tuned Cloudsuite 4.0 workloads to work correctly on trace generation using binary instrumentation, INTEL PIN
• Published in ISCA 2023

Senior Project

• Advised by Prof. Jangwoo Kim, High Performance Computer System Lab @ SNU
• Extended existing gem5 GPU model by duplicating GPUs and rearranging Ruby memory interface
• Modified emulated kernel driver to distinguish GPU ID and doorbell region of each GPU from others

2nd place, 2022 Deep Learning hardware Design Competition

• Organized presentation for special session in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022
• Designed high-performance and power-efficient FPGA implementation for CNN inference
• Designed an adder-tree-based computational unit tailored to Tiny-YOLO v3 model that computes convolutions in parallel and consumes minimal cycles
• Designed the datapath to minimize the buffer usage and maximize computational parallelism, achieving maximum performance with limited on-chip memory